論文

著書(一部)

  • V. VARSHAVSKY, Vуacheslav B. Marakhovsky, Ilya Levin, and Hiroshi Saito, “Hardware Implementation of Fuzzy Controllers”, Fuzzy Controllers, Theory and Applications, February 2011.
  • Cadence, 齋藤 寛(監訳), “TLM-Driven Design and Verification Methodology”
  • VDEC監修, 浅田 邦博、藤田 昌宏共編,齋藤 寛, “システムLSI設計自動化技術の基礎: 5章 非同期論理合成ツールPetrify”, 培風館, pp.44–58, 2005.
  • Masahiro Fujita, Satoshi Komatsu, and Hiroshi Saito, “Dependable Computing Systems: Chapter 1 Formal Verification Techniques for Digital Systems”, Wiley-Interscience, pp.3–25, 2005.

ジャーナル、トランザクション

  1. Hiroshi Saito, Masashi Imai, Tomohiro Yoneda, “Task Allocation Methods based on the Maximum Task Parallelism for Multi-core Systems with the DTTR Scheme,” IEICE Technical Report, VLD2015-113, No.465, pp.13-18, February 2016.
  2. Jukiya Furushima, Masamitsu Nakajima, Hiroshi Saito, “Design of an Asynchronous Processor with Bundled-data Implementation on a Commercial Field Programmable Gate Array”, Informatica 40 (2016), Vol. 40 Issue 4, pp.399–408, December 2016.
  3. Minoru Iizuka, Naohiro Hamada, and Hiroshi Saito, “An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data Implementation”, IEICE Transactions on Electronics, Volume E96-C No.4, pp.482–491, April 2013.
  4. Naohiro Hamada and Hiroshi Saito, “Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation”, IEICE Transaction, Volume E95-C No.4, pp.506–515, April 2012.
  5. Naohiro Hamada, Yuuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, “A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation”, IPSJ Transaction on System LSI Design Methodology, no.2, pp.67–79, Feburary 2009.
  6. V. VARSHAVSKY, Vуacheslav B. Marakhovsky, and Hiroshi Saito, “CMOS Implementation of an Artificial Neuron Training on Logical Threshold Functions”, WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, pp.370–391, Issue 4, Volume 8, April 2009.
  7. V. VARSHAVSKY, Vуacheslav B. Marakhovsky, Ilya Levin, and Hiroshi Saito, “Multiple-valued Logic Approach to Fuzzy Controllers Implementation”, WSEAS TRANSACTIONS on ELECTRONICS, pp.109–133, Issue 6, Volume 4, June 2007.
  8. Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, “Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times”, IEICE Transaction, vol.E90-A, no.12, pp.2790–2799, December 2007.
  9. Takeshi Matsumoto, Hiroshi Saito, and Masahiro Fujita, “An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences”, IEICE Transaction, vol.E88-A, no.12, pp.3315–3323, December 2005.
  10. Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, and Takashi Nanya, “Logic Optimization of Asynchronous Speed-Independent Circuits Using Transduction Methods”, IPSJ Transaction, vol.45, no.5, pp.1289–1299, May 2004.
  11. Nattha Sretasereekul, Hiroshi Saito, Euiseok Kim, Metehan Ozcan, Masashi Imai, Hiroshi Nakamura, and Takashi Nanya, “Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design”, IEICE transaction, vol.E86-A, no.12, pp.3027–3037, December 2003.
  12. Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alex Yakovlev, and Takashi Nanya, “Design of Asynchronous Controllers with Delay Insensitive Interface”, IEICE transaction, vol.E85-A, no.12, pp.2577-2585, December 2002.
  13. Yuuichi Okuyama, Nattha Sretasereek, Hiroshi Saito, Takashi Nanya, and Kenichi Kuroda, “Synthesis of Asynchronous Control Cricutis Based on Hierarchical CDFG”, IPSJ Transaction, vol.43, no.5, pp.1225–1234, May 2002.

国際会議

  1. Taiki Urakawa, Hiroshi Saito, “Design of an Asynchronous Inverse Discrete Cosine Transform Circuit on an FPGA”, Proceedings of the 2nd International Conference on Applications in Information Technology (ICAIT-2016), pp.94–97, October 2016.
  2. Jukiya Furushima, Hiroshi Saito, “FPGA based Design of a Low Power Asynchronous MIPS Processor”, Proceedings of the 2nd International Conference on Applications in Information Technology (ICAIT-2016), pp.98–102, October 2016.
  3. Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, and Kenji Kise, “Dependable Real-Time Task Execution Scheme for a Many-Core Platform,” Proc. 28th edition of the Defect and Fault Tolerance in VLSI and Nanotechnology Systems Symposium, pp. 198-205, October 2015.
  4. Satoru Miyasono, Yousuke Moriai, Hiroshi Saito, “A Code Partitioning Tool for Simulink Models to Implement on FPGA-based Network-on-Chip Architecture”, Proc. IEEE 8th International Symposium on Embedded Multicore Mancore System-on-Chip (MCSoC), pp.141–148, September 2014.
  5. Keitaro Takizawa, Shunya Hosaka, Hiroshi Saito, “A Design Support Tool Set for Asynchronous Circuits with Bundled-data Implementation on FPGAs”,Proc. IEEE 24th International Conference on Field Programmable Logic and Applications (FPL), pp.1–4, September 2014.
  6. Hideki Katabami, Hiroshi Saito, Tomohiro Yoneda, “Design of a GALS-NoC using Soft-cores on FPGAs” Proc. IEEE 7th International Symposium on Embedded Multicore Mancore System-on-Chip (MCSoC), pp.31–36, September 2013.
  7. M.Iizuka, H.Saito, “A floorplan method for ASIC designs of asynchronous circuits with bundled-data implementation” Proc. IEEE 11th International New Circuits and Systems Conference (NEWCAS), pp.1-4, June 2013.
  8. Hiroshi Saito, Tomohiro Yoneda, and Yuichi Nakamura, “An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip”, Proc. IEEE 6th International Symposium on Embedded Multicore System-on-Chip (MCSoC), pp.100–106, Septermber 2012.
  9. Minoru Iizuka, Naohiro Hamada, Hiroshi Saito, Ryoichi Yamaguchi, and Minoru Yoshinaga, “A Tool Set for the Design of Asynchronous Circuits with Bundled-data Implementation”, International Conference on Computer Design, pp.78–83, October 2011.
  10. Naohiro Hamada and Hiroshi Saito, “Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-data Implementation”, GLS VLSI’11 VLSI, pp.157–162, May 2011.
  11. Hiroshi Saito and  Naohiro Hamada, “A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs”, International Symposium on Circuits and Systems (ISCAS), pp.925–928, May 2010.
  12. Naohiro Hamada, Hiroshi Saito, “Iterative Application of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-data Implementation”, The 24th International Technical Conference on Circuits/Systems, Computers and Communications, pp.53–56, July 2009.
  13. Naohiro Hamada, Yuuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, “A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation”, International Conference on Application of Concurrency to System Design, pp.50–55, June 2008.
  14. Takao Konishi, Naohiro Hamada, and Hiroshi Saito, “A Control Circuit Synthesis Method for Asynchronous Circuits in Bundled-Data Implementation”, International Conference on Compute and Information Technology, pp.847–852, October 2007.
  15. Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, “ILP-Based Scheduling for Asynchronous Circuits in Bundled-Data Implementation”, International Conference on Compute and Information Technology, pp.172–177, September 2006.
  16. Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, “A Scheduling Method for Asynchronous Bundled-Data Implementations Based on The Completion of Data Operations”, International Technical Conference on Circuit/Systems, Computers and Communications, pp.433–434, July 2005.
  17. Nattha Jindapetch, Hiroshi Saito, Pornchai Phukapattranont, and Krerkchai Thongnoo, “Area-Speed Ratio Productions for Data-Path Resource Sharing Decisions”, International Technical Conference on Circuit/Systems, Computers and Communications , pp.765–766, July 2005.
  18. Nattha Jindapetch, Hiroshi Saito, Krerkchai Thongnoo, and Takashi Nanya, “A Fair Overhead Comparison between Asynchronous Four-Phase Based Controllers and Local Controllers”, International Conference of Electrical Engineering/Electronics, Computer, Telecommunication, and Information, pp.791–794, May 2005.
  19. Takeshi Matsumoto, Hiroshi Saito, and Masahiro Fujita, “An Equivalence Checking Method for C Descriptions based on Symbolic Simulation with Textual Differences,” Proc. of IASTED International Conference on Advences in Computer Science and Technology , pp.246–251, Nov. 2004.
  20. Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, and Takashi Nanya, “Implementation of a Generalized Synchronous Variable Computation Time Arithmetic Unit with a Single-Dual-Single Wrapper”, In Proc. International Technical Conference on Circuits/Systems, Computersand Communications, pp.1075-1078, July 2003.
  21. Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, and Masahiro Fujita, “Engineering Changes in Field Modifiable Architecture”, In Proc. ACM/IEEE International Conference on Formal Methods and Models for Codesign, pp.87-94, June 2003.
  22. Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, and Takashi Nanya, “Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions”, In Proc. IEEE International Symposium on Asynchronous Circuits and Systems , pp.184–195, May 2003.
  23. Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Ozcan, Krerkchai Thongnoo, Hiroshi Nakamura, and Takashi Nanya, “A Zero-Time-Overhead Asynchronous Four-Phase Controller”, In Proc. IEEE International Symposium on Circuits and Systems , vol.5, pp.205-208, May 2003.
  24. Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretaseereekul, Hiroshi Nakamura, and Takashi Nanya, “Control Signal Sharing of Asynchronous Circuits Using Datapath Delay Information”, In Proc. IEEE International Symposium on Circuits and Systems , vol.5, pp.617-620, May 2003.
  25. Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, and Takashi Nanya, “Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units”, In Proc. Design Automation and Test in Europe, pp.276-281, March 2003.
  26. Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, and Takashi Nanya, “Logic Optimization of Asynchronous SI Controllers using Transduction Method” In Proc. Asia South Pacific Design Automation Conference, pp.197-202, January 2003.
  27. Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, and Takashi Nanya, “Performance optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units” In Proc. Asia South Pacific Design Automation Conference, pp.816-819, January 2003.
  28. Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, and Yoshihisa Kojima, “Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies”, In Proc. Hawaian International Conference on System Sciences, January 2003.
  29. Nattha Sretaseereekul, Yuuichi Okuyama, Hiroshi Saito, Masashi Imai, Kenichi Kuroda, and Takashi Nanya, “Flexible Partitioning of CDFGs for Compact Asynchronous Controllers”, In proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp.1724-1727, July 2002.
  30. Hiroshi Saito, Alex Kondratyev, and Takashi Nanya, “Design of Asynchronous Controllers with Delay Insensitive Interface”, In Proc. Asia South Pacific Design Automation Conference, pp.93-98, January 2002.
  31. Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, and Alex Yakovlev. “What is the cost of delay insensitivity?”, In Proc. IEEE/ACM International Conference on Computer Aided Design, pp.316-323, November 1999.
  32. Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, and Alex Yakovlev, “Bridging modularity and optimality: delay insensitive interfacing in asynchronous circuits synthesis”, In Proc. IEEE Internatinal Conference on Systems, Man, and Cybernetics, pp.899-904, October 1999.

ワークショップ

  1. Kazumasa Yoshimi, Hiroshi Saito, “A Delay Adjustment Method for Asynchronous Circuits with Bundled-data Implementation Considering a Latency Constraint”, The 20th Workshop on Synthesis And System Integration of Mixed Information Technologies(SASIMI)2016, pp.219–224, October 2016.
  2. Shunya Hosaka, Hiroshi Saito, “Constraining Operation Delay for Dynamic Power
    Optimization of Asynchronous Circuits”, International Workshop on Applications in Information Technology (IWAIT-2015), pp.16–20, October 2015.
  3. Hiroshi Saito, Tomohiro Yoneda, Yuichi Nakamura, “A Redundant Task Allocation Method for Reliable Network-on-Chips”, The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies(SASIMI)2015, pp.287–292, Mar 2015.
  4. 熊谷 諒平,飯塚 成,松浦 光児,齋藤 寛, “非同期式AVRプロセッサの設計”,第24回回路とシステムワークショップ, pp.152-157, 2011年 8月.
  5. Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Atasushi Matsumoto, “Achieving Degradation Tolerance in a Hardware Accelerator with Parallel Function Units” Proc. WDSN2009, pp.28–33, Jun 2009.
  6. Hiroshi Saito, Tomohiro Yoneda,and Takashi Nanya, “Evaluation of a Delay Adjustment Method for FPGA Implementation of Asynchronous Circuits with Bundled-data Implementation”, The 22nd Workshop on Circuits and Systems in Karuizawa, pp.201–206, April 2009.
  7. Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, “A Scheduling Method for Asynchronous Bundled-Data Implementations”, International Workshop on Logic and Synthesis, pp.341–348, June 2005. (Poster)
  8. Takeshi Matsumoto, Hiroshi Saito, and Masahiro Fujita, “Equivalence Checking for Transformations and Optimizations in C Programs on Dependence Graphs”, International Workshop on Logic and Synthesis, pp.357–364, June 2005. (Poster)
  9. Takeshi Matsumoto, Hiroshi Saito, and Masahiro Fujita, “An Efficient Equivalence Checking of Similar C Descriptions with Use of the Textual Difference,” Proc. of IEEE/ACM International Workshop on Logic and Synthesis , pp.314–320, June 2004.
  10. Takeshi Matsumoto, Thanyapat Sakunkonchak, Hiroshi Saito, and Masahiro Fujita, “Verification of Behavioral Consistency in C by Using Symbolic Simulation and Program Slicer”, In Proc. International Workshop on Software Model Checking , pp.w80-w84, USA, June 2003.
  11. Takeshi Matsumoto, Hiroshi Saito, and Masahiro Fujita, “Equivalence Checking of C-based Hardware Descriptions by Using Symbolic Simulation and Program Slicing”, In Proc. IEEE/ACM International Workshop on Logic and Synthesis , pp.252-259, USA, May 2003.
  12. Hiroshi Saito, Takaya Ogawa, Thanyapat Sakunkonchak, Masahiro Fujita, and Takashi Nanya, “An Equivalence Checking Methodology for Hardware Oriented C-based Specifications”, In Proc. IEEE International High Level Design Varidation and Test Workshop, pp.139-144, Cannes, France, October 2002.
  13. Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, and Takashi Nanya, “Logic Optimization of Asynchronous SI Controllers using Transduction Method”, In Proc. IEEE/ACM International Workshop on Logic and Synthesis, pp.245-250, New Orleans, LA, June 2002.
  14. Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, and Masahiro Fujita, “Field Modifiable Architecture and its Design Methodology”, In Proc. IEEE/ACM International Workshop on Logic and Synthesis, pp.103-108, New Orleans, LA, June 2002.
  15. Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, and Alex Yakovlev, “What is the cost of delay insensitivity?”, In Proc. International Workshop on Hardware Design and Petri Nets, pp.169-189, Wiliamsburg, VA, June 1999.

ポスター/Work-in-Progress

  1. 仙波 翔吾, 齋藤 寛, “Development of a Transformation Tool for Asynchronous RTL Models”, The International Symposium on Asynchronous Circuits and Systems(ASYNC)2017 Work in Progress, サンディエゴ, 2017年5月
  2. 齋藤 寛, “Arduinoを用いた積雪量を計測するセンサーネットワークの構築”, ASN研究会, 京都, 2014年7月
  3. 齋藤 寛, “Synthesis of an Asynchronous Circuits with Bundled-data Implementation from SystemC Models”, Design Automation Conference(DAC)2014 Work in Progress, サンフランシスコ, 2014年6月
  4. 齋藤 寛, “A Multi-Task Scheduling and Allocation Method for Reliable Network-on-Chip”, Design Automation Conference(DAC)2013 Work in Progress, オースティン, 2013年6月

技術報告

  1. 吉見宗真, 齋藤寛, “束データ方式による非同期式回路の遅延調整に関する考察”, 研究報告システムとLSIの設計技術(SLDM), 2016-SLDM-176, no.4, pp.1–6, 2016年5月.
  2. 保坂隼也, 齋藤寛, “演算の移動度に基づいた束データ方式による非同期式回路の電力最適化手法の評価”, 電子情報通信学会技術研究報告, vol.116, no.478, VLD2016-122, pp.109–114, 2017年3月.
  3. 仙波翔吾, 齋藤寛, “同期式RTLモデルから非同期式RTLモデルへの変換ツールの実装”, 電子情報通信学会技術研究報告, vol.116, no.478, VLD2016-107, pp.31–36, 2017年3月.
  4. 齋藤寛, 今井雅, 米田友洋, “DTTR方式によるマルチコアシステム向けのタスクの最大並列度を基にしたタスク割り当て手法”, 電子情報通信学会技術研究報告, vol.115, no.465, VLD2015–113, pp.13–18, 2016年2月.
  5. 保坂隼也, 齋藤寛, “束データ方式による非同期式回路に対する演算の移動度を利用した動的電力最適化手法の評価”, 電子情報通信学会技術研究報告, 2015-SLDM-173, no.38, pp.201–206, 2015年12月.
  6. 齋藤寛, 今井雅, 米田友洋, “DTTR方式によるマルチコアシステムの信頼性向上のためのタスク割り当て手法の検討”, 電子情報通信学会技術研究報告, 2015-SLDM-172, no.12, pp.63–68, 2015年10月.
  7. 齋藤寛, 米田友洋,今井雅, “Duplication with Temporary Triple Modular Redundancy and Reconfigurationのためのタスク割り当て手法”, DAシンポジウム2015論文集, 2015, pp.5–10, 2015年8月.
  8. 滝澤 恵多郎, 齋藤 寛, “束データ方式による非同期式回路のFPGA設計支援環境の構築”, 研究報告システムとLSIの設計技術(SLDM), 2015-SLDM-171, 5, pp.1–6, 2015年5月.
  9. 小峰 太一, 齋藤 寛, “高位合成ツールからの非同期式回路生成に関する研究”, 電子情報通信学会技術研究報告, vol.114, no.476, VLD2014–165, pp.73–78, 2015年3月.
  10. 森合洋介, 中島正光, 保坂隼也, 小平行秀, 齋藤 寛, “センサーネットワークによる積雪量の可視化”, 電子情報通信学会 総合大会 講演論文集, B-18-40, Vol.B, pp.587, 2015年3月.
  11. 保坂 隼也, 齋藤 寛, “演算の移動度を利用した束データ方式による非同期式回路の電力最適化手法の検討”, 電子情報通信学会技術研究報告, 信学技報, vol. 114, no.328, VLD2014–104, pp.215–220, 2014年11月.
  12. 小峰 太一, 齋藤 寛, “SystemCモデルから束データ方式による非同期式回路を合成する合成フローの提案”, 電子情報通信学会技術研究報告, 信学技報, vol.114, no.59, PP.21–26, 2014年5月.
  13. 滝澤 恵多郎, 齋藤 寛, “FPGAを対象とした束データ方式による非同期式回路の設計支援ツールセット”, 電子情報通信学会技術研究報告, VLD2013–SLDM–163, No.13, pp.69–74, 2013年11月.
  14. 宮囿 悟, 齋藤 寛, “シングルコア向けのコードをNoCに実装するためのコード分割ツールの検討”, 電子情報通信学会技術研究報告, VLD2013–SLDM–163, No.21, pp.113–118, 2013年11月.
  15. 岩崎 翔太郎, 齋藤 寛, “サイクルタイム制約を考慮した低消費電力な束データ方式による非同期式AVRプロセッサの設計”, 電子情報通信学会技術研究報告, VLD2013–SLDM–163, No.28, pp.153–158, 2013年11月.
  16. 飯塚 成, 齋藤 寛, “束データ方式による非同期式回路を対象としたシミュレーテッドアニーリングとシーケンスペアによるフロアプラン手法”, 電子情報通信学会技術研究報告, VLD2013–1–10, pp.7–12, 2013年5月.
  17. 齋藤 寛, 米田 友洋, 中村 祐一, “高度なネットワークオンチップ実現のためのマルチタスクのスケジュールリングとアロケーション”、電子情報通信学会技術研究報告, VLD2012-136–162, pp.61–66, 2013年3月.
  18. 方波見英基, 齋藤 寛, “Altera FPGAにおけるGALS-NoCとその設計方法”, 電子情報通信学会研究会発表, 信学技報, vol.112, no.377, RECONF2012–62, PP.7–12, 2013年1月.
  19. 濱田 尚宏, 齋藤 寛, “束データ方式による非同期式パイプライン回路を対象とした動作合成手法”、電子情報通信学会技術研究報告, VLD2012–59–106, pp.105–110, 2012年11月.
  20. 滝澤恵多郎, 飯塚 成, 齋藤 寛, “束データ方式による非同期式回路のFPGA設計支援ツールセットの構築”, 信学技報, vol. 112, no. 71, VLD2012–9, pp. 49-54, 2012年5月.
  21. 齋藤 寛, 米田 友洋 , 中村 祐一, “整数線形計画問題に基づいたネットワークオンチップにおけるフォールトトレランスのためのタスクの多重割り当て手法”,デザインガイア2011 -VLSI設計の新しい大地, pp.147–152, 2011年 11月.
  22. 熊谷 諒平, 飯塚 成, 松浦 光児, 齋藤 寛, “非同期式AVRプロセッサの設計”, 第37回パルテノン研究会, 152–157, 2011年 9月.
  23. 飯塚 成, 濱田 尚宏, 齋藤 寛 (会津大), 山口 良一, 吉永 稔(ルネサスマイクロシステム), “束データ方式による非同期式回路の設計支援システムの構築”, SLDM研究会, Vol.2011–SLDM–150, No.9, 2011年 5月.
  24. 濱田 尚宏, 齋藤 寛, “束データ方式による非同期式回路を対象とした動作合成とフロアプランの統合”, デザインガイア2010, 2010年 12月.
  25. 齋藤 寛, “非同期式回路の設計技術”, IEICE ESS Fundamentals Review, Vol.3, No.3, pp.3_64–3_70, 2010年 12月.
  26. 米田 友洋, 今井 雅, 齋藤 寛, 松本 敦, “ディペンダブルNOCへの挑戦”, 電子情報通信学会総合大会, Mar, 2009.
  27. 國澤 友紀, 齋藤 寛, “FPGA実装を対象とした束データ方式による非同期式回路の遅延調整手法”, DAシンポジウム2008, pp.253–258, 2008年 8月.
  28. 濱田 尚宏, 志賀 雄城, 小西 隆夫, 齋藤 寛, “束データ方式による非同期式回路を対象とした動作合成システム”, DAシンポジウム2008, pp.259–264, 2008年 8月.
  29. 志賀 雄城, 濱田 尚宏, 小西 隆夫, 齋藤 寛, “ビット長を考慮した束データ方式による非同期式回路の動作合成手法の提案”, DAシンポジウム2007, pp.187–192, 2007年 8月.
  30. 濱田 尚宏, 小西隆夫, 齋藤 寛, 米田 友洋, 南谷 崇, “束データ方式による非同期式回路の動作合成手法の提案”, 電子情報通信学会技術研究報告, VLD2006-63, pp.71–76, 2006年 11月.
  31. 松本 剛史, Thanyapat Sakunkonchak, 齋藤 寛, 小松 聡, 藤田 昌宏, “線形計画法に基づく逐次化を利用したシステムレベル設計での動作並列化前後での等価性検証手法”, DAシンポジウム2006, pp.157–162, 2006年 7月.
  32. 齋藤 寛, 米田 友洋, 南谷 崇, “Integer Linear Programmingを用いた束データ方式による非同期式回路のスケジューリング”, DAシンポジウム2006, pp.43–48, 2006年 7月.
  33. 齋藤 寛, 米田 友洋, 南谷 崇, “Force-Directed Scheduling手法の非同期式回路への適用と評価”, DAシンポジウム2005, pp.37–42, 2005年 8月.
  34. 齋藤 寛, 米田 友洋, “Force-Directed Schedulingアルゴリズムを用いた非同期式データパス回路合成と効率化の検討”, 電子情報通信学会 技術報告, VLD2004-80, pp.115–120, 2004年 11月.
  35. 齋藤 寛, 川鍋 昌紀, 今井 雅, 中村 宏, 南谷 崇, “動作仕様記述からの非同期式制御回路合成手法”, DAシンポジウム2004, pp.289–294, 2004年 7月.
  36. 川鍋 昌紀, 齋藤 寛, 今井 雅, 中村 宏, 南谷 崇, “非同期データパス合成における解探索空間削減手法”, DAシンポジウム2004, pp.295–300, 2004年 7月.
  37. 松本 剛史, 齋藤 寛, 藤田 昌宏, “C言語動作記述の既存RTL用検証ツールを用いた検証の提案”, DAシンポジウム2004, pp.241–246, 2004年 7月.
  38. 松本 剛史, 齋藤 寛, 藤田 昌宏, “C言語を対象とした記述間の差異に基づく効率的な等価性検証手法,” 電子情報通信学会技術研究報告 , Vol. 103, No. 702, pp.61–66, 2004年 3月.
  39. 松本 剛史, 齋藤 寛, 藤田 昌宏, “C言語でのハードウェア記述に対する効率的な等価性検証手法の提案,” 電子情報通信学会技術研究報告 , Vol. 103, No. 40, pp.31–36, 2003年 5月.
  40. 齋藤 寛, Euiseok Kim, 今井 雅, Nattha Sretaseereekul, 中村 宏, 南谷 崇, “Control Signal Sharing for Asynchronous Circuits Using Datapath Delay Information”, IEICE technical report, CPSY2002–11, November 2002.
  41. 齋藤 寛, 中村 宏, 藤田 昌宏, 南谷 崇, “トランスダクション法を用いた非同期制御回路最適化”, IEICE technical report, VLD2002–5, May 2002.

その他

【招待講演】

  • 齋藤 寛(会津大学):”非同期式回路の合成におけるC-to-Silicon Compilerの利用について”、C-to-Silicon Compiler セミナー2014 in 横浜市, イノテックビル, 2014.3.28.
  • 齋藤 寛(会津大学):”高信頼なネットワークオンチップ実現のための設計支援環境の構築”、組込み産業地域交流プラザ 2013 in 仙台市, エルパーク仙台, 2013.7.31.
  • 齋藤 寛(会津大学):”会津大学におけるC-to-Silicon Compilerを用いた設計教育の取り組みについて”、C-to-Silicon Compilerセミナー2012 in 横浜市, イノテックビル, 2012.5.18.
  • 齋藤 寛(会津大学):”FPGAを対象とした束データ方式による非同期式回路の設計”, IEICE Technical Report, VLD2011, pp.157–162, 2011.1.17.

学位論文

2014年

  • Taichi Komine, “Generation of Asynchronous Circuits from a High-Level Synthesis Tool,” master thesis, Mar. 2014.
  • Keitaro Takizawa, “Development and Evaluation of Design Environment for Asynchronous Circuits with Bundled-data Implementation on FPGAs”, master thesis, Mar. 2014.
  • Masamitsu Nakajima, “Debugging of an Asynchronous AVR Processor using Simulation”, graduation thesis, Mar. 2014.
  • Shunya Hosaka, “A Dynamic Power Optimization Method for Asynchronous Circuits with Bundled-data Implementation using Mobility of Operations”, graduation thesis, Mar. 2014.
  • Yosuke Moriai “A Simulation Model to Implement Simulink Models into a Network-on-Chip”, graduation thesis, Mar. 2014.

2013年

  • Shotaro Iwasaki, “Design and Evaluation of a Low Power Asynchronous AVR Processor considering a Cycle Time Constraint”, master thesis, Mar. 2013.
  • Satoru Miyasono, “Development of a Code Partitioning Tool for Network-on-Chip”, master thesis, Mar. 2013.

2012年

  • Shotaro Iwasaki, “Transformation from a Synchronous MIPS Processor to
    an Asynchronous MIPS Processor”, graduation thesis, Mar. 2012.
  • Taichi Komine, “An ASIC Design Support Tool Set for Asynchronous
    Pipelined Circuits with Bundled-Data Implementation”, graduation thesis, Mar. 2012.
  • Keitaro Takizawa, “Development of An FPGA Design Support Tool Set for
    Asynchronous Circuits with Bundled-data Implementation”, graduation thesis, Mar. 2012.

2011年

  • Minoru Izuka, “An ASIC Design Support System for Asynchronous Circuits with Bundled-Data Implementation”, graduation thesis, Mar. 2011.
  • Hideki Katabami, “Designs of OCP Compliant NoC for FPGA”, graduation thesis, Mar. 2011.
  • Ryohei Kumagai, “Design and Optimization of Asynchronous AVR on ASIC”, graduation thesis, Mar. 2011.

2010年

  • Hiroyuki Shimizu, “Design and Evaluation of Synchronous Network-on-Chip Architecture and GALS Architecture”, master thesis, Mar. 2010.
  • Kosuke Hirata, “A Behavioral Synthesis Method for Asynchronous Circuits with Bundled-data Implementations for a Behavioral Description Including Floating Point Operations”, master thesis, Mar. 2010.
  • Yuya Furukawa, “Design and Evaluation of Asynchronous AVR Microcontroller”, master thesis, Mar. 2010.
  • Yuta Horizoe, “A Behavioral Synthesis Method for Asynchronous Circuits with Bundled-data Implementations for a Behavioral Description Including Arrays”, master thesis, Mar. 2010.
  • Hiroto Ida, “Translation of Single-rail Circuits into Dual-rail Asynchronous Circuits”, graduation thesis, Mar. 2010.
  • Atsunori Hirosawa, “Translation of C Language into Haste Language”, graduation thesis, Mar. 2010.
  • Hikaru Matsuura, “Modeling of Asynchronous MIPS Processor Using Haste Language”, graduation thesis, Mar. 2010.
  • Daisuke Yoshida, “Visualization of Behavioral Synthesis for Asynchronous Circuits with Bundled-data Implementation”, graduation thesis, Mar. 2010.

2009年

  • Takao Konishi, “Pipeline Synthesis for Asynchronous Circuits with Bundled-data Implementation”, master thesis, Mar. 2009.
  • Yuuki Shiga, “Bit-width Optimization for Asynchronous Circuits with Bundled-data Implementation”, master thesis, Mar. 2009.
  • Kazuya Enko, “A Floorplan Method for Asynchronous Circuits with Bundled-data Implementation”, graduation thesis, Mar. 2009.
  • Ryo Oouchi, “A Comparison of Energy Consumption between Synchronous Circuit and Asynchronous Circuit”, graduation thesis, Mar. 2009.

2008年

  • Yuki Kunisawa, “A Delay Adjustment Method for Asynchronous Circuits with Bundled-data Implementation targeting at FPGA Implementation”, master thesis, Mar. 2008.
  • Naohiro Hamada, “A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation”, master thesis, Mar. 2008.
  • Ayumi Itou, “Force-directed List Schedulinggraduation for Asynchronous Circuits with Bundled-data Implementations”, graduation research, Mar. 2008.
  • Kosuke Hirata, “A Behavioral Synthesis Method for Asynchronous Circuits with Bundled-data Implementations from Floating Point Operation Descriptions”, graduation research, Mar. 2008.
  • Yuya Furukawa, “An Iterative Resource Allocation Method Using the Properties of FPGAs”, graduation research, Mar. 2008.
  • Yuta Horizoe, “A Behavioral Synthesis Method for Asynchronous Circuits with Bundled-data Implementations from Array Descriptions”, graduation research, Mar. 2008.

2007年

  • Seiichi Sano, “Fuzzy Controller CMOS Hardware Implementation Using Capacitor Based Summing Amplifiers”, master thesis, Mar. 2007.
  • Yasuhiko Murai, “Self-Timed Data Transmission for Onchip Intermodular Communication”, master thesis, Mar. 2007.
  • Makoto Aoki, “A Synthesis Method of Speculative Completion for Asynchronous Circuits in Bundled-Data Implementation”, graduation research, Mar. 2007.
  • Yuuki Shiga, “Behavioral Synthesis for Asynchronous Circuits in Bundled-Data Implementation Considering Resource Bitwidth”, graduation research, Mar. 2007.
  • Sho Shimanuki, “A Design Method for Asynchronous Circuits in Bundled-Data Implementation on Field Programmable Gate Array”, graduation research, Mar. 2007.
  • Hiroyuki Shimizu, “Technology Mapping of Huffman circuits on Field Programmable Gate array”, graduation research, Mar. 2007.
  • Miho Hoshi, “Evaluation of a Behavioral Synthesis Method for Asynchronous Circuits in Bundled-Data Implementation”, graduation research, Mar. 2007.

2006年

  • Vladislav Snegovoy, “Multivalued Logic Approach to Fuzzy Controller Hardware Implementation”, master thesis, Sep. 2006.
  • Yuki Kunisawa, “Implementing Asynchronous Circuits on a Commercial FPGA”, graduation research, Mar. 2006.
  • Yuusuke Nomoto, “Evaluation of Synchronizers for GALS Architectures on a Commercial FPGA”, graduation research, Mar. 2006.
  • Naohiro Hamada, “Considering Register and Multiplexor Costs in Force-Directed Scheduling Algorithm for Asynchronous Circuits”, graduation research, Mar. 2006.
  • Sakae Kawakami, “Evaluation of Force-Directed Scheduling Algorithm for Asynchronous Circuits in Complexity and Optimality”, graduation research, Mar. 2006.
  • Takao Konishi, “Implementation and Evaluation of an Asynchronous Control Circuit Synthesis Method Based on Cell Controllers”, graduation research, Mar. 2006.