Publications

A part of book

  • Cadence, and Hiroshi Saito(translation), “TLM-Driven Design and Verification Methodology”
  • Masahiro Fujita, Satoshi Komatsu, and Hiroshi Saito, “Dependable Computing Systems: Chapter 1 Formal Verification Techniques for Digital Systems”, Wiley-Interscience, pp.3–25, 2005.

Transactions

  1. Minoru Iizuka, Naohiro Hamada, and Hiroshi Saito, “An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data Implementation”IEICE Transactions on Electronics, Volume E96-C No.4, pp.482–491, April 2013.
  2. Naohiro Hamada and Hiroshi Saito, “Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation”, IEICE Transaction, Volume E95-C No.4, pp.506–515, April 2012.
  3. Naohiro Hamada, Yuuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, “A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation”, IPSJ Transaction on System LSI Design Methodology, no.2, pp.67–79, Feburary 2009.
  4. Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, “Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times”, IEICE Transaction, vol.E90-A, no.12, pp.2790–2799, December 2007.
  5. Takeshi Matsumoto, Hiroshi Saito, and Masahiro Fujita, “An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences”, IEICE Transaction, vol.E88-A, no.12, pp.3315–3323, December 2005.
  6. Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, and Takashi Nanya, “Logic Optimization of Asynchronous Speed-Independent Circuits Using Transduction Methods”, IPSJ Transaction, vol.45, no.5, pp.1289–1299, May 2004.
  7. Nattha Sretasereekul, Hiroshi Saito, Euiseok Kim, Metehan Ozcan, Masashi Imai, Hiroshi Nakamura, and Takashi Nanya, “Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design”, IEICE transaction, vol.E86-A, no.12, pp.3027–3037, December 2003.
  8. Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alex Yakovlev, and Takashi Nanya, “Design of Asynchronous Controllers with Delay Insensitive Interface”, IEICE transaction, vol.E85-A, no.12, pp.2577-2585, December 2002.
  9. Yuuichi Okuyama, Nattha Sretasereek, Hiroshi Saito, Takashi Nanya, and Kenichi Kuroda, “Synthesis of Asynchronous Control Cricutis Based on Hierarchical CDFG”, IPSJ Transaction, vol.43, no.5, pp.1225–1234, May 2002.

International Conferences

  1. Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, and Kenji Kise, “Dependable Real-Time Task Execution Scheme for a Many-Core Platform, “Proc. 28th edition of the Defect and Fault Tolerance in VLSI and Nanotechnology Systems Symposium, pp. 198-205, October, 2015.
  2. Satoru Miyasono, Yousuke Moriai, Hiroshi Saito, “A Code Partitioning Tool for Simulink Models to Implement on FPGA-based Network-on-Chip Architecture”, Proc. IEEE 8th International Symposium on Embedded Multicore Mancore System-on-Chip (MCSoC), September 2014.
  3. Keitaro Takizawa, Shunya Hosaka, Hiroshi Saito, “A Design Support Tool Set for Asynchronous Circuits with Bundled-data Implementation on FPGAs”,Proc. IEEE 24th International Conference on Field Programmable Logic and Applications (FPL), September 2014.
  4. Hideki Katabami, Hiroshi Saito, Tomohiro Yoneda, “Design of a GALS-NoC using Soft-cores on FPGAs” Proc. IEEE 7th International Symposium on Embedded Multicore Mancore System-on-Chip (MCSoC), pp.31-36, September 2013.
  5. M.Iizuka, H.Saito, “A floorplan method for ASIC designs of asynchronous circuits with bundled-data implementation” Proc. IEEE 11th International New Circuits and Systems Conference (NEWCAS), pp.1-4, June 2013.
  6. Hiroshi Saito, Tomohiro Yoneda, and Yuichi Nakamura, “An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip”, Proc. IEEE 6th International Symposium on Embedded Multicore System-on-Chip (MCSoC), Septermber 2012.
  7. Minoru Iizuka, Naohiro Hamada, Hiroshi Saito, Ryoichi Yamaguchi, and Minoru Yoshinaga, “A Tool Set for the Design of Asynchronous Circuits with Bundled-data Implementation”, International Conference on Computer Design, pp.78–83, October 2011.[PDF]
  8. Naohiro Hamada and Hiroshi Saito, “Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-data Implementation”, GLS VLSI’11 VLSI, pp.157–162, May 2011.[PDF]
  9. Hiroshi Saito and  Naohiro Hamada, “A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs”, International Symposium on Circuits and Systems (ISCAS), pp.925–928, May 2010.[PDF]
  10. Naohiro Hamada, Hiroshi Saito, “Iterative Application of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-data Implementation”, The 24th International Technical Conference on Circuits/Systems, Computers and Communications, pp.53–56, July 2009.
  11. Naohiro Hamada, Yuuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, “A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation”, International Conference on Application of Concurrency to System Design, pp.50–55, June 2008.
  12. Takao Konishi, Naohiro Hamada, and Hiroshi Saito, “A Control Circuit Synthesis Method for Asynchronous Circuits in Bundled-Data Implementation”, International Conference on Compute and Information Technology, pp.847–852, October 2007.
  13. Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, “ILP-Based Scheduling for Asynchronous Circuits in Bundled-Data Implementation”, International Conference on Compute and Information Technology, September 2006.
  14. Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, “A Scheduling Method for Asynchronous Bundled-Data Implementations Based on The Completion of Data Operations”, International Technical Conference on Circuit/Systems, Computers and Communications, pp.433–434, July 2005.
  15. Nattha Jindapetch, Hiroshi Saito, Pornchai Phukapattranont, and Krerkchai Thongnoo, “Area-Speed Ratio Productions for Data-Path Resource Sharing Decisions”, International Technical Conference on Circuit/Systems, Computers and Communications , pp.765–766, July 2005.
  16. Nattha Jindapetch, Hiroshi Saito, Krerkchai Thongnoo, and Takashi Nanya, “A Fair Overhead Comparison between Asynchronous Four-Phase Based Controllers and Local Controllers”, International Conference of Electrical Engineering/Electronics, Computer, Telecommunication, and Information, pp.791–794, May 2005.
  17. Takeshi Matsumoto, Hiroshi Saito, and Masahiro Fujita, “An Equivalence Checking Method for C Descriptions based on Symbolic Simulation with Textual Differences,” Proc. of IASTED International Conference on Advences in Computer Science and Technology , pp.246–251, Nov. 2004.
  18. Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, and Takashi Nanya, “Implementation of a Generalized Synchronous Variable Computation Time Arithmetic Unit with a Single-Dual-Single Wrapper”, In Proc. International Technical Conference on Circuits/Systems, Computersand Communications, pp.1075-1078, July 2003.
  19. Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, and Masahiro Fujita, “Engineering Changes in Field Modifiable Architecture”, In Proc. ACM/IEEE International Conference on Formal Methods and Models for Codesign, pp.87-94, June 2003.
  20. Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, and Takashi Nanya, “Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions”, In Proc. IEEE International Symposium on Asynchronous Circuits and Systems , pp.184–195, May 2003.
  21. Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Ozcan, Krerkchai Thongnoo, Hiroshi Nakamura, and Takashi Nanya, “A Zero-Time-Overhead Asynchronous Four-Phase Controller”, In Proc. IEEE International Symposium on Circuits and Systems , vol.5, pp.205-208, May 2003.
  22. Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretaseereekul, Hiroshi Nakamura, and Takashi Nanya, “Control Signal Sharing of Asynchronous Circuits Using Datapath Delay Information”, In Proc. IEEE International Symposium on Circuits and Systems , vol.5, pp.617-620, May 2003.
  23. Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, and Takashi Nanya, “Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units”, In Proc. Design Automation and Test in Europe, pp.276-281, March 2003.
  24. Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, and Takashi Nanya, “Logic Optimization of Asynchronous SI Controllers using Transduction Method” In Proc. Asia South Pacific Design Automation Conference, pp.197-202, January 2003.
  25. Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, and Takashi Nanya, “Performance optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units” In Proc. Asia South Pacific Design Automation Conference, pp.816-819, January 2003.
  26. Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, and Yoshihisa Kojima, “Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies”, In Proc. Hawaian International Conference on System Sciences, January 2003.
  27. Nattha Sretaseereekul, Yuuichi Okuyama, Hiroshi Saito, Masashi Imai, Kenichi Kuroda, and Takashi Nanya, “Flexible Partitioning of CDFGs for Compact Asynchronous Controllers”, In proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp.1724-1727, July 2002.
  28. Hiroshi Saito, Alex Kondratyev, and Takashi Nanya, “Design of Asynchronous Controllers with Delay Insensitive Interface”, In Proc. Asia South Pacific Design Automation Conference, pp.93-98, January 2002.
  29. Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, and Alex Yakovlev. “What is the cost of delay insensitivity?”, In Proc. IEEE/ACM International Conference on Computer Aided Design, pp.316-323, November 1999.
  30. Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, and Alex Yakovlev, “Bridging modularity and optimality: delay insensitive interfacing in asynchronous circuits synthesis”, In Proc. IEEE Internatinal Conference on Systems, Man, and Cybernetics, pp.899-904, October 1999.

Workshops

  1. Hiroshi Saito, Tomohiro Yoneda, Yuichi Nakamura, “A Redundant Task Allocation Method for Reliable Network-on-Chips”, Proc. of The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies(SASIMI) 2015, pp.287–292, Mar 2015.
  2. Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Atasushi Matsumoto, “Achieving Degradation Tolerance in a Hardware Accelerator with Parallel Function Units” Proc. WDSN2009, pp.28–33, Jun, 2009 (査読有)
  3. Hiroshi Saito, Tomohiro Yoneda,and Takashi Nanya, “Evaluation of a Delay Adjustment Method for FPGA Implementation of Asynchronous Circuits with Bundled-data Implementation”, The 22nd Workshop on Circuits and Systems in Karuizawa, pp.201–206, April 2009.
  4. Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, “A Scheduling Method for Asynchronous Bundled-Data Implementations”, International Workshop on Logic and Synthesis, pp.341–348, June 2005. (Poster)
  5. Takeshi Matsumoto, Hiroshi Saito, and Masahiro Fujita, “Equivalence Checking for Transformations and Optimizations in C Programs on Dependence Graphs”, International Workshop on Logic and Synthesis, pp.357–364, June 2005. (Poster)
  6. Takeshi Matsumoto, Hiroshi Saito, and Masahiro Fujita, “An Efficient Equivalence Checking of Similar C Descriptions with Use of the Textual Difference,” Proc. of IEEE/ACM International Workshop on Logic and Synthesis , pp.314–320, June 2004.
  7. Takeshi Matsumoto, Thanyapat Sakunkonchak, Hiroshi Saito, and Masahiro Fujita, “Verification of Behavioral Consistency in C by Using Symbolic Simulation and Program Slicer”, In Proc. International Workshop on Software Model Checking , pp.w80-w84, USA, June 2003.
  8. Takeshi Matsumoto, Hiroshi Saito, and Masahiro Fujita, “Equivalence Checking of C-based Hardware Descriptions by Using Symbolic Simulation and Program Slicing”, In Proc. IEEE/ACM International Workshop on Logic and Synthesis , pp.252-259, USA, May 2003.
  9. Hiroshi Saito, Takaya Ogawa, Thanyapat Sakunkonchak, Masahiro Fujita, and Takashi Nanya, “An Equivalence Checking Methodology for Hardware Oriented C-based Specifications”, In Proc. IEEE International High Level Design Varidation and Test Workshop, pp.139-144, Cannes, France, October 2002.
  10. Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, and Takashi Nanya, “Logic Optimization of Asynchronous SI Controllers using Transduction Method”, In Proc. IEEE/ACM International Workshop on Logic and Synthesis, pp.245-250, New Orleans, LA, June 2002.
  11. Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, and Masahiro Fujita, “Field Modifiable Architecture and its Design Methodology”, In Proc. IEEE/ACM International Workshop on Logic and Synthesis, pp.103-108, New Orleans, LA, June 2002.
  12. Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, and Alex Yakovlev, “What is the cost of delay insensitivity?”, In Proc. International Workshop on Hardware Design and Petri Nets, pp.169-189, Wiliamsburg, VA, June 1999.

Poster

  1. Hiroshi Saito, “Development of a Sensor Network to Measure Snow Depth using Arduino”, IEICE-ASN, Kyoto, July 30th, 2014.
  2. Hiroshi Saito, ”Synthesis of an Asynchronous Circuits with Bundled-data Implementation from SystemC Models”, Design Automation Conference(DAC)2014 Work in Progress, San Francisco, USA, June 1st, 2014
  3. Hiroshi Saito, ”A Multi-Task Scheduling and Allocation Method for Reliable Network-on-Chip”, Design Automation Conference(DAC)2013 Work in Progress, Austin, USA, June 5th, 2013

Thesis

2014

  • Taichi Komine, “Generation of Asynchronous Circuits from a High-Level Synthesis Tool,” master thesis, Mar. 2014.
  • Keitaro Takizawa, “Development and Evaluation of Design Environment for Asynchronous Circuits with Bundled-data Implementation on FPGAs”, master thesis, Mar. 2014.
  • Masamitsu Nakajima, “Debugging of an Asynchronous AVR Processor using Simulation”, graduation thesis, Mar. 2014.
  • Shunya Hosaka, “A Dynamic Power Optimization Method for Asynchronous Circuits with Bundled-data Implementation using Mobility of Operations”, graduation thesis, Mar. 2014.
  • Yosuke Moriai “A Simulation Model to Implement Simulink Models into a Network-on-Chip”, graduation thesis, Mar. 2014.

2013

  • Shotaro Iwasaki, “Design and Evaluation of a Low Power Asynchronous AVR Processor considering a Cycle Time Constraint”, master thesis, Mar. 2013.
  • Satoru Miyasono, “Development of a Code Partitioning Tool for Network-on-Chip”, master thesis, Mar. 2013.

2012

  • Shotaro Iwasaki, “Transformation from a Synchronous MIPS Processor toan Asynchronous MIPS Processor”, graduation thesis, Mar. 2012.
  • Taichi Komine, “An ASIC Design Support Tool Set for AsynchronousPipelined Circuits with Bundled-Data Implementation”, graduation thesis, Mar. 2012.
  • Keitaro Takizawa, “Development of An FPGA Design Support Tool Set forAsynchronous Circuits with Bundled-data Implementation”, graduation thesis, Mar. 2012.

2011

  • Shotaro Iwasaki, “Transformation from a Synchronous MIPS Processor to an Asynchronous MIPS Processor”, Graduation Research, Mar. 2012.
  • Taichi Komine, “An ASIC Design Support Tool Set for Asynchronous Pipelined Circuits with Bundled-Data Implementation”, Graduation Research, Mar. 2012.
  • Keitaro Takizawa, “Development of An FPGA Design Support Tool Set for Asynchronous Circuits with Bundled-data Implementation”, Graduation Research, Mar. 2012.

2010

  • Minoru Izuka, “An ASIC Design Support System for Asynchronous Circuits with Bundled-Data Implementation”, Graduation Research, Mar. 2011.
  • Hideki Katabami, “Designs of OCP Compliant NoC for FPGA”, Graduation Research, Mar. 2011.
  • Ryohei Kumagai, “Design and Optimization of Asynchronous AVR on ASIC”, Graduation Research, Mar. 2011.

2009

  • Hiroyuki Shimizu, “Design and Evaluation of Synchronous Network-on-Chip Architecture and GALS Architecture”, Master Thesis, Mar. 2010.
  • Kosuke Hirata, “A Behavioral Synthesis Method for Asynchronous Circuits with Bundled-data Implementations for a Behavioral Description Including Floating Point Operations”, Master Thesis, Mar. 2010.
  • Yuya Furukawa, “Design and Evaluation of Asynchronous AVR Microcontroller”, Master Thesis, Mar. 2010.
  • Yuta Horizoe, “A Behavioral Synthesis Method for Asynchronous Circuits with Bundled-data Implementations for a Behavioral Description Including Arrays”, Master Thesis, Mar. 2010.
  • Hiroto Ida, “Translation of Single-rail Circuits into Dual-rail Asynchronous Circuits”, Graduation Research, Mar. 2010.
  • Atsunori Hirosawa, “Translation of C Language into Haste Language”, Graduation Research, Mar. 2010.
  • Hikaru Matsuura, “Modeling of Asynchronous MIPS Processor Using Haste Language”, Graduation Research, Mar. 2010.
  • Daisuke Yoshida, “Visualization of Behavioral Synthesis for Asynchronous Circuits with Bundled-data Implementation”, Graduation Research, Mar. 2010.

2008

  • Takao Konishi, “Pipeline Synthesis for Asynchronous Circuits with Bundled-data Implementation”, Master Thesis, Mar. 2009.
  • Yuuki Shiga, “Bit-width Optimization for Asynchronous Circuits with Bundled-data Implementation”, Master Thesis, Mar. 2009.
  • Kazuya Enko, “A Floorplan Method for Asynchronous Circuits with Bundled-data Implementation”, Graduation Thesis, Mar. 2009.
  • Ryo Ouchi, “A Comparison of Energy Consumption between Synchronous Circuit and Asynchronous Circuit”, Graduation Thesis, Mar. 2009.

2007

  • Yuki Kunisawa, “A Delay Adjustment Method for Asynchronous Circuits with Bundled-data Implementation targeting at FPGA Implementation”, Master Thesis, Mar. 2008.
  • Naohiro Hamada, “A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation”, Master Thesis, Mar. 2008.
  • Ayumi Itou, “Force-directed List Schedulinggraduation for Asynchronous Circuits with Bundled-data Implementations”, Graduation Research, Mar. 2008.
  • Kosuke Hirata, “A Behavioral Synthesis Method for Asynchronous Circuits with Bundled-data Implementations from Floating Point Operation Descriptions”, Graduation Research, Mar. 2008.
  • Yuya Furukawa, “An Iterative Resource Allocation Method Using the Properties of FPGAs”, Graduation Research, Mar. 2008.
  • Yuta Horizoe, “A Behavioral Synthesis Method for Asynchronous Circuits with Bundled-data Implementations from Array Descriptions”, Graduation Research, Mar. 2008.

2006

  • Seiichi Sano, “Fuzzy Controller CMOS Hardware Implementation Using Capacitor Based Summing Amplifiers”, Master Thesis, Mar. 2007.
  • Yasuhiko Murai, “Self-Timed Data Transmission for Onchip Intermodular Communication”, Master Thesis, Mar. 2007.
  • Makoto Aoki, “A Synthesis Method of Speculative Completion for Asynchronous Circuits in Bundled-Data Implementation”, Graduation Research, Mar. 2007.
  • Yuuki Shiga, “Behavioral Synthesis for Asynchronous Circuits in Bundled-Data Implementation Considering Resource Bitwidth”, Graduation Research, Mar. 2007.
  • Sho Shimanuki, “A Design Method for Asynchronous Circuits in Bundled-Data Implementation on Field Programmable Gate Array”, Graduation Research, Mar. 2007.
  • Hiroyuki Shimizu, “Technology Mapping of Huffman circuits on Field Programmable Gate array”, Graduation Research, Mar. 2007.
  • Miho Hoshi, “Evaluation of a Behavioral Synthesis Method for Asynchronous Circuits in Bundled-Data Implementation”, Graduation Research, Mar. 2007.

2005

  • Vladislav Snegovoy, “Multivalued Logic Approach to Fuzzy Controller Hardware Implementation”, Master Thesis, Sep. 2006.
  • Yuki Kunisawa, “Implementing Asynchronous Circuits on a Commercial FPGA”, Graduation Research, Mar. 2006.
  • Yuusuke Nomoto, “Evaluation of Synchronizers for GALS Architectures on a Commercial FPGA”, Graduation Research, Mar. 2006.
  • Naohiro Hamada, “Considering Register and Multiplexor Costs in Force-Directed Scheduling Algorithm for Asynchronous Circuits”, Graduation Research, Mar. 2006.
  • Sakae Kawakami, “Evaluation of Force-Directed Scheduling Algorithm for Asynchronous Circuits in Complexity and Optimality”, Graduation Research, Mar. 2006.
  • Takao Konishi, “Implementation and Evaluation of an Asynchronous Control Circuit Synthesis Method Based on Cell Controllers”, Graduation Research, Mar. 2006.