CV for Hiroshi Saito

extensions hair   ,
human hair wigs for black women   ,
Lace Front Wigs    /
human hair extensions   ,
clip in hair extensions   ,
best hair extensions   ,
african american wigs   ,
remy hair extensions   ,
clip in hair extensions   ,
human hair extensions   ,
full lace wigs   ,
Lace Front Wigs   ,
best hair extensions   ,
remy hair extensions   ,
extensions hair   ,
human hair wigs for black women   ,
extensions hair    |
remy hair extensions    |
best hair extensions   ,
hair extensions   ,
full lace wigs   ,
clip in hair extensions   ,
human hair extensions   ,
human hair wigs for black women   ,
human hair wigs   ,
extensions hair   ,
remy hair extensions   ,
hair extensions   ,
african american wigs   ,
clip in extensions   ,
human hair wigs for black women   ,
human hair extensions   ,
best hair extensions   ,
full lace wigs   ,
extensions hair   ,
lace front wigs   ,
african american wigs   ,
clip in hair extensions   ,
human hair wigs for black women   ,
human hair extensions   ,
full lace wigs   ,
best hair extensions   ,
lace front wigs   ,
extensions hair   ,
african american wigs   ,
remy hair extensions   ,
human hair wigs for black women   ,
hair extensions   ,
human hair wigs   ,
full lace wigs   ,
best hair extensions   ,
human hair wigs for black women   ,
extensions hair   ,
hair extensions   ,
remy hair extensions   ,
human hair wigs   ,
hair extensions   ,
full lace wigs   ,
clip in hair extensions   ,
lace front wigs   ,
clip in extensions   ,
african american wigs   ,
best hair extensions   ,
human hair wigs for black women   ,
extensions hair   ,
human hair wigs   ,
remy hair extensions   ,
hair extensions   ,
full lace wigs   ,
clip in hair extensions   ,
lace front wigs   ,
human hair wigs   ,
human hair wigs for black women   ,
best hair extensions   ,
african american wigs   ,
human hair extensions   ,
human hair wigs for black women    ,
  • Education Background
  • ■ Bachelor, The University of Aizu, 1998
    ■ Master, The University of Aizu, 2000
    ■ Ph.D., The University of Tokyo, 2003

  • Working Experience
  • April 2003 – March 2004: Research associate, Research Center for Advanced Science and Technology, The University of Tokyo
    April 2008 – March 2010: Visiting researcher, Research Center for Advanced Science and Technology, The University of Tokyo
    April 2004 – March 2011: Assistant professor, The University of Aizu
    April2012 – Current: Senior associate professor, The University of Aizu

  • Belonging Society
  • IEICE, IPSJ, IEEE, ACM

  • Executive Positions in the Academic Societies, Etc.
  • Societies:
    2006 – 2009: IPSJ Tohoku branch, committee member
    2004 – 2007: IPSJ SIGSLDM, committee member

    Editor:
    2007 – 2010: IPSJ transaction on System-Level Design Methodology, associate editor

    Conferences:
    2009 – 2012: International Symposium on Embedded Multicore System-on-chip, program committee, financial co-chair (2012)
    2010 Asia South Pacific Design Automation Conference, program committee
    2009: 19th Intelligent System Symposium, publication co-chair
    2008: 14th IEEE International Symposium on Asynchronous Circuits and Systems, program committee
    2006 – 2008: IEEE International Conference on Computer and Information Technology, program committee, publication co-chair (2007)

    Others:
    2007, 2010-2012: Asia South Pacific Design Automation Conference Student Forum, committee member
    2006, 2008: ISPJ Tohoku branch workshop in Aizu, local arrangement
    2008: ACM ICPC Asia regional in Aizu, committee member
    2007: IPSJ SIGSLDM workshop in Aizu, local arrangement
    2005: IPSJ SIGSLDM DA symposium, committee member

  • Research Achievements
  • Summary of research achievements

    1. High-level synthesis for NoC architectures
    This is a part of “Development of a Dependable Network-on-Chip Platform” supported by JST/CREST/DVLSI from 2008 – 2013 (5.5 years project)

    Abstract:
    In this project, we are going to research high-level synthesis for network-on-chip. Network-on-chips (NoCs) which organize a network on a chip and connect processing cores through the network are paid attention for interconnection of a large system. As wires are divided by routers, wire loads can be suppressed into small size. Also, as each core communicates in parallel through the network by representing data into packets, high throughput will be realized.
    In NoCs, it is very important to decide when and how tasks which organize applications are executed and allocated. Especially, it is critical for applications that the real-time execution must be guaranteed. Also, it is very important to guarantee that the application is running even though some cores are failed from the point of reliability.
    This project develops a high-level synthesis system which maps tasks of a given application to network-on-chip considering constraints such as the memory size and dependability.

    2. Development of a design support system for asynchronous circuits with bundled-data implementation
    This is a joint work with Renesus Micro Systems from 2010 under NDA.

    Abstract:
    In this project, we develop a design support system for asynchronous circuits with bundled-data implementation. Compared to synchronous circuits which are controlled by global clock signals, asynchronous circuits are controlled by pairs of local handshake signals. Because of the absence of global clock signals, asynchronous circuits do not have problems related to clock signals such as clock skew, power consumption on the clock network, and so on. However, the design of asynchronous circuits is more difficult than synchronous ones. For the designs of asynchronous circuits, designers need to select appropriate delay model, data encoding scheme, and control protocol according to applications. Unfortunately, design method and design constraints are different according to the selection. Also, hazard-free implementation is required. To solve design difficulty, design automation of asynchronous circuits is indispensable.
    In this project, we are going to develop a set of tools which support the design of asynchronous circuits with bundled-data implementation. The key concept is that design processes which cannot be supported by the current design automation tools such as timing analysis are automated by this tool set. Doing so, the most of design processes after register transfer level can be fully automated.
    Currently, we distributed this tool set to Renesus Micro Systems. Then, we have a plan to use this tool set for their commercial products.

    3. Optimization of energy consumption for asynchronous circuits with bundled-data implementation considering the freedom of execution times
    This work is partially supported by the Ministry of Education, Culture, Sports, Science and Technology, Grant-in-Aid for Young Scientists (B) from 2009 to 2011.

    Abstract:
    In this project, we are going to develop a design support tool to optimize energy consumption for asynchronous circuits with bundled-data implementation. In cases of synchronous circuits, the execution of operations is restricted by not only data dependency between operations but also clock cycle time. On the other hand, the execution of operations in asynchronous circuits is restricted by data dependency between operations only. This implies that designers can allocate the execution time of operations. Therefore, compared to synchronous circuits, asynchronous circuits have more freedom for the execution timing of operations.
    In this project, we are going to develop a design method which minimizes energy consumption while maximizing such freedom by changing resources to slow and low power ones, inserting operand isolators, and allocating lower supply voltage for operations in the non-critical path. Then, we are going to develop a design support tool which implements the proposed method. Finally, we are going to evaluate the proposed method with the comparison for synchronous circuits.

    4. Behavioral synthesis for asynchronous circuits with bundled-data implementation
    This work was partially supported by the Ministry of Education, Culture, Sports, Science and Technology, Grant-in-Aid for Young Scientists (B) 18700047 (2006 – 2008) and 16700050 (2004 – 2005)

    Abstract:
    In this project, we developed a behavioral synthesis system for asynchronous circuits with bundled-data implementation. This tool accepts a behavioral description of an application in C language, a set of design constraints, and a resource library. Then, based on time constraint or resource constraint, this tool decides the schedule of operations, the allocation of resources, and the synthesis of the control circuit. The main difference from behavioral synthesis systems for synchronous circuits is operation scheduling. In cases of synchronous circuits, operations are scheduled to clock cycle times. On the other hand, operations for bundled-data implementation are scheduled by approximating the start times of operations calculated by the completion times of preceding operations.
    Currently, we extend the proposed system to deal with more syntax in C language and to optimize the performance using a floorplan method. Also, we extend the proposed system to generate a script which is used for lower level of design such as logic synthesis and physical synthesis. Finally, we are going to apply the proposed system for realistic designs.

  • Teaching Experience and Educational Achievements
  • Courses in charge:
    Undergraduate school, the University of Aizu
    ■ Logic circuit design (lec, ex), 2004 (ex only), 2005 (ex only), 2006, 2007, 2008, 2009, 2010, 2011
    ■ Advanced logic circuit design (lec, ex), 2008, 2009, 2010, 2011
    ■ Computer architecture (ex), 2004, 2005, 2006, 2007
    ■ Automata & languages (lec, ex), 2004 (ex only), 2005 (ex only), 2006, 2007
    ■ Computer organization and design (ex), 2004

    The number of class teaching hours per week:
    2011: 1st 3h, 2nd 4.5h, 2010: 1st 3h, 2nd 4.5h, 2009: 1st 3h, 2nd 4.5h,
    2008: 1st 3h, 2nd 4.5h, 2007: 1st 6h, 2nd 4.5h, 2006: 1st 6h, 2nd 4.5h,
    2005: 1st 4.5h, 2nd 3h, 2004: 1st 4.5h, 2nd 6h
    Graduate school, the University of Aizu
    ■ Introduction to computer-aided design of integrated circuits I (Theory of advanced logic devices -> Introduction to computer-aided design of integrated circuits -> current) , 2006, 2007, 2008, 2009, 2010, 2011
    ■ Introduction to computer-aided design of integrated circuits II, 2009, 2010, 2011
    ■ Creative factory seminar, 2006, 2007, 2008, 2009, 2010, 2011

    The number of class hours per week:
    2011: 1st 3h, 2nd 1.5h, 3rd 3h, 2010: 1st 3h, 2nd 1.5h, 3rd 3h,
    2009: 1st 3h, 2nd 1.5h, 3rd 3h, 2008: 2nd 1.5h, 3rd 3h,
    2007: 2nd 1.5h, 3rd 3h, 2006: 2nd 1.5h, 3rd 3h

  • Project Achievements
  • 1. High-level synthesis for NoC architectures
    This is a part of “Development of a Dependable Network-on-Chip Platform” supported by JST/CREST/DVLSI from 2008 – 2013 (5.5 years project)

    2. Development of a design support system for asynchronous circuits with bundled-data implementation
    This is a joint work with Renesus Micro Systems from 2010 under NDA.

    3. Optimization of energy consumption for asynchronous circuits with bundled-data implementation considering the freedom of execution times
    This work is partially supported by the Ministry of Education, Culture, Sports, Science and Technology, Grant-in-Aid for Young Scientists (B) from 2009 to 2011.

    4. Behavioral synthesis for asynchronous circuits with bundled-data implementation
    This work was partially supported by the Ministry of Education, Culture, Sports, Science and Technology, Grant-in-Aid for Young Scientists (B) 18700047 (2006 – 2008) and 16700050 (2004 – 2005)